This invention relates to semiconductor memory devices and, more particularly, to minimizing energy requirements for integrated circuit memories such as Dynamic Random Access Memories (DRAMs).
In general, semiconductor memory devices such as DRAMs are formed from sub-arrays, or banks, of memory cells. For example, a four-megabit DRAM may be formed on a chip using four banks, each bank including one million memory cells.
The memory cells of each array bank are formed in rows and columns. Each memory cell in a row is connected to a conductive row line and each memory cell in a column is connected to at least one conductive column line. Row addresses are applied to the row lines and column addresses are applied to the column lines for the purpose of storing and reading digital data in the memory cells and, in the case of DRAMs, refreshing the memory cells. The digital data is sensed by sense amplifiers connected to the column lines of each bank. For example, 4096 sense amplifiers are required for a four-megabit DRAM having four banks, each bank having 1024 columns of cells and 1024 rows of cells.
The number of row address bits received by a DRAM from a microprocessor may, by industry standard, be equal to the number of column address bits. For example, the row address signals and the column address signals furnished by a microprocessor to a four-megabit DRAM may each have 11 bits. However, if that same four-megabit DRAM includes four array banks, each bank having 1024 columns and 1024 rows of memory cells, then the information from the column address bits and from the row address bits must be redefined to conform to the array bank configuration. In redefining the bits, one or more of the row bits may be assigned to address one or more columns in a bank or banks of cells. Similarly, one or more of the column bits may be assigned to designate a particular bank in which data may be stored or read.